? semiconductor components industries, llc, 2016 november, 2016 ? rev. 11 1 publication order number: nid9n05cl/d NID9N05ACL, nid9n05bcl power mosfet 9.0 a, 52 v, n?channel, logic level, clamped mosfet w/esd protection in a dpak package benefits ? high energy capability for inductive loads ? low switching noise generation features ? diode clamp between gate and source ? esd protection ? hbm 5000 v ? active over?v oltage gate to drain clamp ? scalable to lower or higher r ds(on) ? internal series gate resistance ? aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? automotive and industrial markets: solenoid drivers, lamp drivers, small motor drivers maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain?to?source voltage internally clamped v dss 52?59 v gate?to?source voltage ? continuous v gs 15 v drain current ? continuous @ t a = 25 c drain current ? single pulse (t p = 10 s) i d i dm 9.0 35 a total power dissipation @ t a = 25 c p d 1.74 w operating and storage temperature range t j , t stg ?55 to 175 c single pulse drain?to?source avalanche energy ? starting t j = 125 c (v dd = 50 v, i d(pk) = 1.5 a, v gs = 10 v, r g = 25 ) e as 160 mj thermal resistance, junction?to?case junction?to?ambient (note 1) junction?to?ambient (note 2) r jc r ja r ja 5.2 72 100 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. when surface mounted to a fr4 board using 1 pad size, (cu area 1.127 in 2 ). 2. when surface mounted to a fr4 board using minimum recommended pad size, (cu area 0.412 in 2 ). device package shipping ? ordering information dpak case 369c style 2 m pwr drain (pins 2, 4) source (pin 3) gate (pin 1) marking diagram y = year ww = work week xxxxx = 05acl or 05bcl g = pb?free package r g overvoltage protection esd protection www. onsemi.com 1 = gate 2 = drain 3 = source 4 = drain 1 2 3 4 yww d9n xxxxxg v dss (clamped) r ds(on) typ i d max (limited) 52 v 90 m 9.0 a ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. NID9N05ACLt4g dpak (pb?free) 2500/tape & reel dpak (pb?free) 2500/tape & reel nid9n05bclt4g
NID9N05ACL, nid9n05bcl www. onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?to?source breakdown voltage (note 3) (v gs = 0 v, i d = 1.0 ma, t j = 25 c) (v gs = 0 v, i d = 1.0 ma, t j = ?40 c to 125 c) temperature coefficient (negative) v (br)dss 52 50.8 ? 55 54 ?10 59 59.5 ? v v mv/ c zero gate voltage drain current (v ds = 40 v, v gs = 0 v) (v ds = 40 v, v gs = 0 v, t j = 125 c) i dss ? ? ? ? 10 25 a gate?body leakage current (v gs = 8 v, v ds = 0 v) (v gs = 14 v, v ds = 0 v) i gss ? ? ? 22 10 ? a on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 100 a) threshold temperature coefficient (negative) v gs(th) 1.3 ? 1.75 ?4.5 2.5 ? v mv/ c static drain?to?source on?resistance (note 3) (v gs = 4.0 v, i d = 1.5 a) (v gs = 3.5 v, i d = 0.6 a) (v gs = 3.0 v, i d = 0.2 a) (v gs = 12 v, i d = 9.0 a) (v gs = 12 v, i d = 12 a) r ds(on) ? ? ? 70 67 153 175 ? 90 95 181 364 1210 ? ? m forward transconductance (note 3) (v ds = 15 v, i d = 9.0 a) g fs ? 24 ? mhos dynamic characteristics input capacitance (v ds = 40 v, v gs = 0 v, f = 10 khz) c iss ? 155 250 pf output capacitance c oss ? 60 100 transfer capacitance c rss ? 25 40 input capacitance (v ds = 25 v, v gs = 0 v, f = 10 khz) c iss ? 175 ? pf output capacitance c oss ? 70 ? transfer capacitance c rss ? 30 ? switching characteristics (note 4) turn?on delay time (v gs = 10 v, v dd = 40 v, i d = 9.0 a, r g = 9.0 ) t d(on) ? 130 200 ns rise time t r ? 500 750 turn?off delay time t d(off) ? 1300 2000 fall time t f ? 1150 1850 turn?on delay time (v gs = 10 v, v dd = 15 v, i d = 1.5 a, r g = 2 k ) t d(on) ? 200 ? ns rise time t r ? 500 ? turn?off delay time t d(off) ? 2500 ? fall time t f ? 1800 ? turn?on delay time (v gs = 10 v, v dd = 15 v, i d = 1.5 a, r g = 50 ) t d(on) ? 120 ? ns rise time t r ? 275 ? turn?off delay time t d(off) ? 1600 ? fall time t f ? 1100 ? gate charge (v gs = 4.5 v, v ds = 40 v, i d = 9.0 a) (note 3) q t ? 4.5 7.0 nc q 1 ? 1.2 ? q 2 ? 2.7 ? product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NID9N05ACL, nid9n05bcl www. onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise noted) characteristic unit max typ min symbol switching characteristics (note 4) gate charge (v gs = 4.5 v, v ds = 15 v, i d = 1.5 a) (note 3) q t ? 3.6 ? nc q 1 ? 1.0 ? q 2 ? 2.0 ? source?drain diode characteristics forward on?voltage (i s = 4.5 a, v gs = 0 v) (note 3) (i s = 4.0 a, v gs = 0 v) (i s = 4.5 a, v gs = 0 v, t j = 125 c) v sd ? ? ? 0.86 0.845 0.725 1.2 ? ? v reverse recovery time (i s = 4.5 a, v gs = 0 v, di s /dt = 100 a/ s) (note 3) t rr ? 700 ? ns t a ? 200 ? t b ? 500 ? reverse recovery stored charge q rr ? 6.5 ? c esd characteristics electro?static discharge capability human body model (hbm) esd 5000 ? ? v machine model (mm) 500 ? ? product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NID9N05ACL, nid9n05bcl www. onsemi.com 4 typical performance curves 0 0.15 12 10 0.1 0.05 0 614 0.2 0.35 16 2.5 1.5 1 0.5 100 10,000 1,000,000 08 8 2 1 v ds , drain?to?source voltage (volts) i d , drain current (amps) 0 v gs , gate?t o?source voltage (volts) figure 1. on?region characteristics figure 2. transfer characteristics i d , drain current (amps) 2 0.3 10 8 0.1 0 612 figure 3. on?resistance versus gate?to?source voltage v gs , gate?t o?source voltage (volts) figure 4. on?resistance versus drain current and gate voltage i d , drain current (amps) r ds(on) , drain?to?source resistance ( ) r ds(on) , drain?to?source resistance ( ) figure 5. on?resistance variation with temperature t j , junction temperature ( c) figure 6. drain?to?source leakage current versus voltage v ds , drain?to?source voltage (volts) r ds(on) , drain?to?source resistance (normalized) i dss , leakage (na) 18 ?50 50 25 0 ?25 75 125 100 16 40 30 20 5 0 3 4 12 8 v v ds 10 v t j = 25 c t j = ?55 c t j = 100 c v gs = 12 v 150 175 v gs = 0 v i d = 9 a v gs = 12 v 16 0.2 0.5 v gs = 10 v i d = 4.5 a t j = 25 c t j = 150 c t j = 100 c 4 0 16 8 12 4 t j = 25 c 45 1000 6.5 v 5 v 4 v 3.8 v 4567 23 5 0.4 0.25 0.3 2 6 2 10 14 6 v t j = 25 c 4.6 v 4.2 v 3.4 v 3.2 v 2.8 v 6 2 18 10 14 9 78 4 v gs = 4 v 28 41 8 0.4 100,000 25 35
NID9N05ACL, nid9n05bcl www. onsemi.com 5 typical performance curves c rss 020304050 v ds , drain?to?source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 200 0 300 100 10 v gs = 0 v t j = 25 c c oss c iss 400 500 frequency = 10 khz v ds v gs 10 0 0.4 drain?to?source diode characteristics v sd , source?to?drain voltage (volts) figure 8. gate?to?source and drain?to?source voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 11010 0 10,000 100 t, time (ns) v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current v gs , gate?t o?source voltage (volts) 0 5 3 1 0 q g , total gate charge (nc) 4 2 3 12 5 1.2 2 4 6 i d = 9 a t j = 25 c q gd q gs q t t r t d(off) t d(on) t f 1000 v dd = 40 v i d = 9 a v gs = 10 v 4 8 1.0 0.8 0.6 50 40 30 20 10 0 v ds , drain?to?source voltage (volts)
NID9N05ACL, nid9n05bcl www. onsemi.com 6 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy , avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. figure 11. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain?to?source voltage (volts) figure 12. thermal response 1 100 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.1 10 10 v gs = 12 v single pulse t c = 25 c 1 ms 100 s 10 ms dc 10 s r(t), effective transient thermal resistance (normalized) t, time (s) 0.1 1.0 0.01 0.2 d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 110 0.1 0.01 0.001 0.0001 0.00001 0.1
NID9N05ACL, nid9n05bcl www. onsemi.com 7 package dimensions dpak (single gauge) case 369c issue f 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* b d e b3 l3 l4 b2 m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.028 0.045 0.72 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 7. optional mold feature. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.114 ref 2.90 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw e bottom view z bottom view side view top view alternate constructions note 7 z on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nid9n05cl/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?
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